1. Field of the Invention
The present invention relates to a memory device and a method for manufacturing the same, and more particularly, to a flash memory device having a lightly doped source and a method for manufacturing the same.
2. Description of the Related Art
A typical structure of arranging nonvolatile memory cells is disclosed in "A SINGLE TRANSISTOR EPROM CELL AND ITS IMPLEMENTATION IN A 512K CMOS EEPROM", IDEM pp 616-619, 1985. FIG. 1 is a sectional view of a conventional nonvolatile Erasable and Programmable Read Only Memory (EPROM) type NOR flash memory cell. Referring to FIG. 1, a first insulating layer 330, a floating gate 340, a second insulating layer 350 and a control gate 360 are sequentially formed on a semiconductor substrate 300. Also, a drain 310 and sources 320 and 322 are formed in a predetermined region under the surface of the semiconductor substrate 300. The source comprises a highly doped region 320 and a lightly doped region 322 surrounding the highly doped region 320. The lightly doped region 322 and the highly doped region 320 are partially overlapped by the floating gate 340. Also, the drain 310 is doped with a high concentration impurity, and the drain 310 is partially overlapped by the floating gate 340. The first insulating layer 330 is formed of a tunnel oxide layer in which electrons can be tunneled.
Operation of an EPROM type NOR flash memory cell will be described below. The EPROM type NOR flash memory cell has programming, erasing and reading operations. When a high voltage is applied to a bit line connected to the drain 310 and to a word line connected to the control gate 360 to program a cell, hot electrons are generated at the drain junction. The hot electrons pass through the first insulating layer 330 and then are injected into the floating gate 340 arid thus the hot electrons are stored in the floating gate 340. Accordingly, the threshold voltage of a device is increased, so that the device is programmed. The electrons stored in the floating gate 340 must be removed to erase the programmed device. When a high voltage is applied to the source, the electrons stored in the floating gate move to the source in a Fowler-Nordheim (F-N) tunneling manner to be erased from the floating gate 340.
Accordingly, the program operation of a nonvolatile memory device is performed by electron injection in the drain 310. Here, the electrons injected into the floating gate 340 are partially trapped by the first insulating layer 330. Characteristics of the first insulating layer 330 are deteriorated by the trapped electrons. Also, the erasing operation of the device is performed through the source. Here, the tunneled electrons are trapped by the first insulating layer 330 formed between the floating gate 340 and the sources 322 and 320, and thereby deteriorate the characteristics of the device.
The size of a cell is reduced to realize high-integration of a nonvolatile memory device. However, the drain 310 requires a depletion region for generating hot-carriers under the floating gate 340, so that the drain 310 and the floating gate 340 must overlap each other. Also, in order to lower the applied voltage during the erase operation, the highly doped source must partially overlap the floating gate 340 to directly tunnel the carriers. Also, in order to prevent the generation of the breakdown in the highly doped source 320 by the applied voltage during the erase operation, a lightly doped source 322 must surround the highly doped source 320. Moreover, an effective channel length between the source and the drain 310 under the floating gate 340 is required, so that the channel is capable of operating as a memory device, as well as in a region where the source and the drain 310 overlap the floating gate 340. Therefore, the integration of the nonvolatile memory device is reduced.
FIG. 2 is a sectional view of a memory cell in which a highly doped source 320 and a floating gate 340 overlap each other. Reference numeral 324 indicates a depletion region formed in a junction region of the lightly doped source 322 and the semiconductor substrate 300 when a voltage is applied to the source for the erase operation. Here, electrons stored in the floating gate 340 tunnel to the source as indicated by the arrows. Thus, in a memory cell in which the highly doped source 320 and the floating gate 340 overlap with each other, a low voltage is applied to the source to cause electron tunneling. If the highly doped source 320 does not overlap with the floating gate 340, electrons stored in the floating gate 340 tunnel through the depletion region to the highly doped source 320. Thus, in a memory cell in which the highly doped source 320 and the floating gate 340 do not overlap with each other, a high voltage must be applied to the highly doped source to cause electron tunneling. It is preferable that the highly doped source 320 and the floating gate 340 overlap with each other to lower the applied voltage during the erase operation. Thus, in a memory cell in which the electrons stored in the gate are erased in the F-N tunneling manner, each of the highly doped source 320 and drain 310 must overlap with the floating gate 340, so that it is difficult to increase the integration of the nonvolatile memory device.
An EPROM having a lightly doped source is disclosed in U.S. Pat. No. 4,652,897. The structure of a device disclosed in the U.S. Pat. No. 4,652,897 will be described with reference to FIGS. 3 and 4. Referring to FIG. 3, a first insulating layer 510, a floating gate 340, a second insulating layer 350 and a control gate 360 are sequentially stacked on a semiconductor substrate 300. Also, a drain 310, a lightly doped source 502 and a highly doped source 500 are formed around the surface of the semiconductor substrate 300. Here, the impurity concentration of the lightly doped source is 1.times.10.sup.16.about.1.times.10.sup.17 atoms/cm.sup.3, and the length W1 along the gate of FIG. 3 is 0.3.about.0.4 .mu.m. The drain 310 and the lightly doped source 502 are overlapped by the floating gate 340. The first insulating layer 510 is a gate oxide layer.
FIG. 4 is a graph showing the electric field intensity b1 and potential a1 in a cell during programming of a memory cell. Referring to FIG. 4, it can be shown that the electric field intensity b1 is increased in the lightly doped source 502 having a high resistance. Thus, in the memory cell of FIG. 3, hot-carriers generated in the lightly doped source 502 are then injected into the floating gate 340, to thereby program the memory cell. Also, in the memory cell of FIG. 3, an electric erase operation cannot be performed and thus the electrons stored in the floating gate 340 are erased by exposing them to ultra-violet light.
FIG. 5 is a sectional view of a memory cell in which electrons stored in the floating gate 340 can be electrically erased through a source. Referring to FIG. 5, a gate oxide layer 512 and a tunnel oxide layer 514 are formed instead of the first insulating layer 330 of FIG. 3. Thus, the program operation is the same as that of the memory cell disclosed in FIG. 3, but the erase operation is electrically performed through the source. That is, when a high voltage is applied to the highly doped source 500 in an erase operation, the electrons stored in the floating gate 340 move across the tunnel oxide layer 514 by tunneling.
However, in the memory cell disclosed in FIG. 5, the highly doped source 500 and the floating gate 340 do not overlap with each other. Thus, in order to cause tunneling of the electrons stored in the floating gate 340, a relatively high voltage must be applied to the highly doped source 500 considering the resistance and the depletion region in the lightly doped source 502, so that the memory cell has operational requirements which are difficult to meet. Also, a high electric field is applied to the lightly doped source 502 during the erase operation, so that many hot carriers are generated in the lightly doped source 502 and thus the number of traps between the tunnel oxide layer 514 and the lightly doped source 502 are increased. Thus, resistance of the memory cell is increased, so that characteristics of the memory cell are changed.